Jump along with instructions (LDA, ADD, SUB, OUT, HLT) of SAP-01 force computer to repeat or skip part of a program which opens up a new world for computer program.
SAP - 01 & SAP-02 architechture
difference between sap-1 and sap-2
| Difference | SAP-01 | SAP-02 |
|---|---|---|
| Bus Width | 8 bit | 16 bit |
| Use of Bidirectional Register | No | Yes |
| Program Counter address length/ address length received by MAR | 4 bit (unidirectional pc) | 16 bit (bidirectional pc) |
| Data Length | 8 bit | 8 bit |
| Opcode length | 4 bit | 8 bit |
| Input port | Input is attached with MAR. | pin 01 is used for hexadecimal input. pin 02 is used for binary input |
| Output port | output register is present. | pin 03 is used for hexadecimal output. pin 04 is used for binary output. |
| Display | Binary | Hexadecimal |
| memory data register (MDR) | NO | Yes, holds the data temporarily |
| Possible No of Instructions | 2^4=16 | 2^8=256. though only 42 instructions are there in sap-2 |
| memory size | 16x8 bit = 16 Byte | 64 KB (2 KB for ROM <0000H-07FFH>, 62 KB for RAM<08FFH,FFFFH>) |
| Address and Data flow | Address is passed through MAR to RAM. | Address is passed through MAR and then into 64 KB memory. Data is given as input in the MDR. |
| Flags | works for sign flag and zero flag only | |
| LDA instruction | 1 byte (0000 0001 - opcode and address) | 3 byte (1 byte for opcode, 2 byte for address) |
Bidirectional Registers
In SAP-1, instruction register needs 8 wires (seperate 4 wires for receiving 4 bit input data from bus, and seperate 4 wires for storing 4 bit output data into the bus) In SAP-2, bidirectional registers are used which require 4 wires for both 4 bit input and output data. The I/O pins are connected internally. As both input data and output data are received/stored with the same 4 wires, less wire is used than SAP-1. hence less capacitance is produced and the circuit is also less complex than sap-1.
To reduce wiring capacitance of sap-02 we will run only one set of wires between each register and the bus. The input and output pins are shorted. Only one group of wires are connected to the bus. During a computer run, either LOAD or ENABLE is active, but not both at the same time. An active LOAD means a binary word flows from bus to register input. The output lines are floating. An active ENABLE means a binary word flows from register to the bus. The input lines are floating. The input output pins are connected shortly which reduces number of i/o pins and also the wiring capacitance. bidirectional means data can move either way.
Memory Reference Instructions
Memory reference instruction(MRI) is one that uses the memory during the execution cycle. Memory reference instructions are relatively slow because they require more than one memory access during the instruction cycle. Furthermore, we often want to move data directly from one register to another not going through memory. MOV stands for move. It tells computer to move data from one register to another.
| Cycle | States | State Name |
|---|---|---|
| T1 | Address | |
| Fetch | T2 | Increment |
| T3 | Memory |
Hand Assemble
Hand assemble means to translate a source program to machine language program by hand rather than machine. Hand assemble the below program
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MVI A, 17H
MVI B, 2DH
ADD B
STA 5600H
INR A
MOV C,A
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MVI A,00H
MVI B,0CH
MVI C, 08H
REPEAT: ADD B
DCR C
JZ DONE
JMP REPEAT
DONE: HLT
Change the multiplication part into a subroutine located at starting address F006H.
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REPEAT: ADD B
DCR C
JNZ REPEAT
RET
MVI A,00H
MVI B,0CH
MVI C, 08H
CALL F006H
HLT
| Instruction | Program |
|---|---|
| load the accumulator with the contents of memory location 2000H. | LDA 2000H |
| store the accumulator content at memory location 7FFFH. If A=8AH, after execution of STA 7FFFH, memory address 7FFFH will store 8AH. | STA 7FFFH |
| load the accumulator with 37H. | MVI A, 37H (move immediate) MVI A, byte MVI B, byte MVI C, byte |
| Show the mnemonics for a program that loads the accumulator with 49H, B register with 4AH, C register with 4BH, then store the accumulator content at location 6285H. | MVI A, 49H MVI B, 4AH MVI C, 4BH STA 6285H HLT |
| A=34H B=05H After MOV A,B A=05H B=05H | |
| ADD stands for add the data in the designated register to the contents of accumulator. | |
| Similarly, SUB means subtract the data in the designated register from the accumulator content. | |
| Show the mnemonic for adding decimal 23 and 45. the answer is to be stored at location 5600H. Also increment the answer by 1 and store it in C register. | MVI A, 17H MVI B, 2DH ADD B STA 5600H INR A MOV C,A |
| Get the next instruction from memory location 3000H.JMP is the mnemonic for Jump.Every JMP instruction includes an address that is loaded into the program counter. It tells the computer to get the next instruction from the designated memory location. | JMP 3000H |
| During the execution of a instruction, if the accumulator contents become negative, it gets the next instruction from memory location 3000H if sign flag=1. JM is the mnemonic for jump if minus. The computer will jump to designated address if and only if sign flag (S) is set (1). S=0, if A ≥ 0 1, if A < 0 | JM 3000H |
| JZ is the mnemonic for jump if zero. JNZ stands for jump if not zero. During execution, if accumulator becomes zero, the zero flag will be set (Z=1). JM, JZ, JNZ are conditional jumps. JMP is unconditional. | |
| Show a program that multiple decimal 12 and 8. | MVI A,00H MVI B,0CH MVI C, 08H REPEAT: ADD B DCR C JZ DONE JMP REPEAT DONE: HLT MVI A,00H MVI B,0CH MVI C, 08H REPEAT: ADD B DCR C JNZ REPEAT HLT |
| – Complement the accumulator – Inverts each bit of the accumulator | CMA |
| And the accumulator content with the designated register | ANA B |
| Or the accumulator content with the designated register | ORA B |
| Xor the accumulator content with the designated register | XRA B |
| And immediate. And the accumulator contents with the byte that immediately follows the opcode. | ANI C7H |
| – Or immediate – Or the accumulator contents with the byte that immediately follows the opcode. | ORI C7H |
| – Xor immediate – Xor the accumulator contents with the byte that immediately follows the opcode. | XRI C7H |
| – Stands for no operation. – During execution of NOP, all T states do nothings, no register changes occur. | NOP |
| It ends data processing | HLT |
| Tells computer to take data from designated port to the accumulator. IN byte(port number) | IN 01H IN 02H |
| Accumulator word is loaded into the designated output port. OUT byte(port number) | OUT 03H & OUT 04H |
| Rotate the accumulator left. Will shift all bits to the left and move MSB into LSB. | RAL |
| Rotate the accumulator right. | RAR |
| Take input from port 2 and determine whether the LSB is 0 or 1. – If 0, then load ASCII value of Y to the accumulator – else load ASCII value of N to accumulator | IN 02H ANI 01H JZ YES MVI A, 4EH (4EH is ASCII of N) JMP DONE YES: MVI A, 59H (59H is ASCII of Y) DONE: OUT 03H HLT |
| Modify the previous program if we want serial output at port 4 instead of parallel output at port 3. | IN 02H ANI 01H JZ YES MVI A, 4EH (4EH is ASCII of N) JMP DONE YES: MVI A, 59H (59H is ASCII of Y) DONE: MVI C, 08H AGAIN: OUT 04H RAR DEC C JNZ AGAIN HLT |
CALL & RET
CALL is the mnemonic for call the subroutine. A subroutine is a program stored in memory for possible use by various programs. Like finding sines, cosines, tangents, square roots etc. Every call instruction must include the starting address of the desired subroutine.
CALL 5000H
RET stands for return. It is used at the end of the subroutine. When CALL is executed automatically PC contents are stored in FFFEH and FFFFH (last two memory locations). CALL is unconditional.
HANDSHAKING
Handshaking is an interaction between a CPU and a peripheral device during an I/O data transfer. If input is told to be taken from port 01 then handshaking is must.
- Input from port 01 will not be taken until The LSB of port 2, also called the ready bit goes high.
- The time which is wasted to check the LSB of port 02 until it becomes high is called CPU waiting.
- LSB=1 of port 02 means input is available at port 01.
- After taking input from port 01, the 7th pin or acknowlegde bit (MSB) of port 4 goes high, automatically resettng the ready bit at port 02.
- ACK=1 of port 04 means “input is received”, the message which is acknowlegded by keyboard encoder allowing it to reset the ready bit.
- And then the ACK bit gets reset.
- If again any input is available at port 01, the ready bit at port 02 goes high. Thus the process of handshaking continues.
The sequence of SAP-2 handshaking: i. READY bit goes high. ii. Input the data from port 1. iii. ACK bit goes high to reset the READY bit. iv. Reset the ACK bit.
Take a input from port 1 using handshaking.
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AGAIN: IN 02H
ANI 01H
JZ AGAIN // input from port 02 is continuously taken until ready bit goes high.
IN 01H // after ready bit went high, input from port 01 is taken
MOV B,A // the value of accumulator would change so better store it to another register
MVI A, 80H // the ack bit goes high in order to give keyboard encoder the message that the input is received.
OUT 04H
MVI A, 00H // the ack bit is reset.
OUT 04H
HLT
T States
- Variable machine cycle.
- any register instruction takes 4 T states.
- any MRI takes 7 T states.
- JM/JZ/JNZ has T states of 10/7. 10 T states when jump occurs. 7 T states when jump does not occur.
| Instructions | States | Bytes |
|---|---|---|
| ADD, MOV, SUB, INR, DCR, ANA, ORA, XRA, CMA | 4 | 1 |
| ANI, MVI, ORI, XRI | 7 | 2 |
| LDA, STA | 13 | 3 |
| CALL | 18 | 3 |
| JMP | 10 | 3 |
| JZ, JNZ, JM | 10 (if jump happens) / 7 (if jump doesn’t happen) | 3 |
| RET | 10 | 1 |
| NOP | 4 | 1 |
| HLT | 5 | 1 |
| RAR, RAL | 4 | 1 |
| IN, OUT | 10 | 2 |
FLAGS
- If all the output bits of the accumulator are sent to NOR gate, then the result of NOR gate is sent to zero flag. If all the pins were 0, output of NOR=1, otherwise in all cases output of NOR=0. so when NOR=1 and lf=1 only then the zero flag will be affected.
- The MSB of the accumulator is sent to AND gate with the other input Lf, if both are 1, the output of AND=1, meaning sign bit is high. So the Sign flag becomes 1.
- We get to know whether the flags are being affected or not from Lf pin. if Lf=0 zero flag and sign flag will not be affected, if Lf=1 both will be affected.
Addressing modes
Direct addressing - LDA/STA/IN/OUT
Immediate addressing - MVI/ANI/ORI/XRI/CALL/JMP/JZ/JNZ/JM
Register addressing - ADD/SUB/INR/DCR/MOV/ANA/ORA/XRA
Implied addressing - CMA/RAR/RAL/RET
SAP-2 has a clock frequency of 1 MHz. This means each T state is 1 microsecond long. How long does it take to execute the following SAP-2 subroutine?
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bytes Program T-states
_____ _______________________ ________________________________________________________________________________________________________________________
2 MVI C, 46H (decimal 70) // jekono immediate instruction er jonno 7 ta T state lage. so 1 (execute time) * 7 * 1 microsec.
1 AGAIN: DCR C // jekono register instruction er jonno 4 ta T state lage. so 70 * 4 * 1 microsec.
3 JNZ AGAIN // 70 tomo bar e giye C=0 jokhon hobe tokhon JNZ kaj korbe na so JNZ execute hobe 69 times so, 69 * 10 * 1 microsecs.
ar execute hobe na 1 times so, 1 * 7 * 1 microsecs.
1 NOP // 1 * 4 * 1 microsecs
1 RET // 1* 10 * 1 microsecs.
_____ _______________________ _____________________________________________________
8 total = 998 microsecs
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bytes Program T-states
_____ _______________________ ________________________________________________________________________________________________________________________
2 MVI B, 0AH 1*7*1 = 7
2 LOOP 1: MVI C, 47H (decimal 71) 10*7*1 = 70
1 LOOP 2: DCR C 10*(71*4*1) = 2840
3 JNZ LOOP2 10*(70*10*1 + 1*7*1) = 7070
1 DCR B 10*4*1 = 40
3 JNZ LOOP1 9*10*1 + 1*7*1 = 97
1 RET 1*10*1 = 10
_____ _______________________ ________________________________________________________________________________________________________________________
13 total = 10134 microsecs
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bytes Program T-states
_____ _______________________ ________________________________________________________________________________________________________________________
2 MVI B, 0AH 1*7*1 = 7
2 LOOP 1: MVI C, 47H (decimal 71) 10*7*1 = 70
1 LOOP 2: DCR C 10*(71*4*1) = 2840
2 MVI A,5 10*(71*7*1) = 4970
1 LOOP 3: DCR A (10*71)*(5*4*1) = 14200
3 JNZ LOOP3 (10*71)*(4*10*1 + 1*7*1) = 33370
3 JNZ LOOP2 10*(70*10*1 + 1*7*1) = 7070
1 DCR B 10*4*1 = 40
3 JNZ LOOP1 9*10*1 + 1*7*1 = 97
1 RET 1*10*1 = 10
_____ _______________________ ________________________________________________________________________________________________________________________
19 total = 62674 microsecs